The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for efficiently storing meta-bits within a system memory.
There is a growing trend for microprocessors to include many cores. A multi-core processor is a single computing component with two or more independent actual processors (called “cores”), which are the units that read and execute program instructions. The instructions are ordinary central processor unit (CPU) instructions, such as add, move data, and branch, but the multiple cores can run multiple instructions at the same time, increasing overall speed for programs amenable to parallel computing. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP), or onto multiple dies in a single chip package.
In computing, symmetric multiprocessing (SMP) involves a multiprocessor computer hardware architecture where two or more processors are connected to a single shared main memory and are controlled by a single OS instance. In the case of multi-core processors, the SMP architecture may apply to the cores, treating them as separate processors. When an SMP system is built from multiple core chips, a significant burden is placed on coherent interconnect design and technology to provide for growing snoop bandwidth requirements. Wider interconnects result in more complex and expensive processor modules and system boards, which results in greater snoop bandwidth.
Cache coherency refers to the consistency of data stored in local caches of a shared resource. When components in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of processing units in a multiprocessing system. If a first processing core has a copy of a memory block from a previous read and a second processing core changes that memory block, the first processing could be left with an invalid cache of memory without any notification of the change. Cache coherency is intended to manage such conflicts and maintain consistency between cache and memory.